The present invention is directed to bus systems, more particularly to improved methods and arrangements for providing clock signals in multiple channel modules and bus systems.
Conventional bus systems are typically implemented in single channel architectures. While conventional bus systems have been implemented using modules, the modules in such systems have merely been arranged in a serial relationship on a motherboard. For example, consider the bus system shown in FIG. 1. This bus system is characterized by a master 11 mounted on a motherboard 10. A number of connectors 13 are also mounted on motherboard 10. Each connector 13 is adapted to receive a module 14 comprising one or more integrated circuits 15. Thus, by means of a connector 13, a module 14 is mechanically mounted and electrically connected within the bus system.
One or more bus(es) 16 forms the communications channel between master 11 and a termination resistor 12. Bus 16 typically comprises a number of signals lines communicating control information, address information, and/or data. The signal lines forming bus 16 traverse the motherboard and/or the modules to electrically connect the integrated circuits 15 to master 11.
There are numerous problems associated with such conventional bus systems. For example, the serial arrangement of the connectors and associated modules creates a relatively lengthy communications channel. Since there are many factors limiting the maximum practical length of a communications channel, channel length should, wherever reasonably possible, be minimized.
Conventional bus systems are also characterized by numerous electrical connection points between the connectors and the bus portions traversing the motherboard, between the modules and the connectors, and between the integrated circuits and the bus portion traversing the modules. Improperly matched electrical connections often produce impedance discontinuities that tend to degrade signal transmission characteristics on the bus. Accordingly, the number of impedance discontinuities associated with the bus connections should be minimized.
Such conventional bus systems present a very static architecture, which may not lend itself to the efficient utilization of available space within a larger system. For example, a maximum, pre-set number of connectors is typically provided within the conventional bus system, regardless of the actual number of modules initially contemplated for the bus system. Upgrading the bus system to include additional modules requires that a sufficient number of connectors be provided up to the maximum length (or capacity) of the channel. Typically, empty connectors are filled with dummy modules until they are needed. Absent these spare connectors, upgrading the bus system to include an additional module would require that the motherboard be replaced.
The static architecture of the conventional bus system provides a xe2x80x9cone size fits allxe2x80x9d approach to larger systems incorporating the bus system. The serial arrangement of connectors and modules on a motherboard may produce an undesirably large footprint within the larger system. Further, this configuration does not lend itself to irregular or crowded spaces within the larger system.
Of further concern is the routing of clock signals. High-speed clock signals require special treatment, in that they are particularly susceptible to reflections based on discontinuities in the clock loop circuit. Thus, there is a need for improved clock routing schemes that can support, not only static architectures, but also modular architectures.
The present invention provides improved clock routing methods and arrangements suitable for use with modular components.
The above stated needs and others are met, for example, by an apparatus that includes a memory interface circuit, a clock signal generating circuit, and a plurality of memory circuits. The memory circuits are operatively coupled and arranged in an order on a plurality of memory modules, such that the memory module positioned at the beginning of the order is coupled to an output of the clock signal generating circuit and the memory interface circuit. The memory module that is positioned at the end of the order is unique in that it includes a clock signal terminating circuit connected to the last memory integrated circuit. With this configuration, a clock loop is formed by directly routing the clock signal from the output of the clock signal generating circuit through each of the memory modules in the order (without connecting to any of the intervening memory integrated circuits) to the memory integrated circuit positioned at the end of the order. Then, the clock signal is asserted on the previous memory modules by routing it back through the memory integrated circuits thereon, in reverse order to the memory integrated circuit positioned at the beginning of the order and from there to the memory interface circuit. To complete the clock loop, the clock signal is again asserted by routing it from the memory interface circuit back through the memory integrated circuits in order to the memory integrated circuit positioned at the end of the order. Finally, the clock signal is terminated at the clock signal terminating circuit on the memory module positioned at the end of the order.
By employing certain layouts, the memory module positioned at the end of the order can be moved between various positions depending upon the number/arrangement of memory integrated circuits. For example, a terminating memory module may be the only memory module in the order, at which point it can be operatively configured in a first slot of a multiple slot arrangement. However, should additional memory modules be required this terminating memory module can be moved to a slot firer in the order to allow for the additional memory modules there between. Certain exemplary configurations of such arrangements are shown in the detailed description. These exemplary implementations have a three-slot order. However, those skilled in the art will recognize that orders of three or greater slots/memory modules can be supported by the clock routing schemes in accordance with the present invention.